The present invention relates to communication systems and, more particularly, circuit for correcting DC offset and signal processing apparatus using thereof.
Direct conversion receiver has been developed and applied for many years. In the direct conversion receiver, an input radio signal is down converted to a base band signal without being converted to intermediate frequency (IF) signal. If direct conversion receiver is used, the number of exterior devices can be reduced. Additionally, the amount of digital signal processing is relatively small. Therefore, direct conversion receiver is advantageous because of low cost and being lightness in weight. Further, it is possible to make one chip receiver if direct conversion is used.
FIG. 1 shows a block diagram of a conventional direct conversion receiver.
As shown in FIG. 1, the conventional direct conversion receiver comprises a low noise amplifier 101, a mixer 103, an amplifier 105, a filter 107, and a variable gain amplifier 109.
Low noise amplifier 101 is a variable gain amplifier. It receives radio signal via antenna to amplify the radio signal while suppressing noise. Mixer 103 mixes the output signal of low noise amplifier 101 with local oscillation signal LO and, thereby, outputs base band signal. Amplifier 105 amplifies the base band signal output from mixer 103. Filter 107 selects desired signal from the amplified signal. Variable gain amplifier 109 amplifies the output signal of filter 107 while varying the gain of the output signal in order to maintain the required power level of the output signal.
The direct conversion receiver shown in FIG. 1 has advantages of reduced exterior device and small amount of digital signal processing as described above. However, it suffers from DC offset problem resulting difficulty in being implemented in integrated circuitry.
Primary cause for the DC offset in a direct conversion receiver is the local oscillator leakage. Specifically, leakage of the input radio signal appears at one of the input of the mixer to which local oscillation signal LO is inputted. The leakage components are driven to the mixer 103 together with local oscillation signal LO. Consequently, the input radio signal is mixed with the leakage components of itself at mixer 103. Similarly, leakage of local oscillation signal LO appears at the input of the mixer to which input radio signal is inputted. The leakage components are driven to the mixer 103 together with the input radio signal. Consequently, local oscillation signal LO is mixed with the leakage components of itself at mixer 103. The mixing of signals having identical frequency characteristic results in DC offset at the output of mixer 103. The DC offset resulting from the mixing of signals having identical frequency characteristic is called DC offset by self-mixing. The quantity of DC offset by self-mixing varies continuously in accordance with power level and frequency of input radio signal and local oscillation signal LO.
Secondary cause for DC offset is mismatch of load at output terminal of mixer 103 and duty error of local oscillation signal LO being inputted to mixer 103.
The other cause for DC offset is mismatch of devices in amplifier and filters. This DC offset varies in accordance with variation of cutoff frequency of filter 107 and gain of variable gain amplifier 109.
DC offset of direct conversion receiver results from a lot of causes as described above. The amount of DC offset varies continuously in accordance with the variation of frequency of local oscillation signal, input radio signal, gain of amplifiers.
The DC offset problem is one of the major reasons causing deterioration of direct conversion receiver""s performance. In this regard, there are a lot of efforts to solve the DC offset problem.
A direct conversion receiver in accordance with one of those efforts is described in U.S. patent application Ser. No. 2002/0094788 published on Jul. 18, 2002 with a title of xe2x80x9cSignal processing semiconductor integrated circuit device and wireless communication systemxe2x80x9d by Norio Hayashi, et al. FIG. 2 shows a block diagram illustrating the direct conversion receiver described in U.S. patent application Ser. No. 2002/0094788. The direct conversion receiver comprises a dummy low noise amplifier (LNA) 112B, programmable gain amplifiers PGA1-PGA3, and low pass filters LPF1-LPF3. DC offset appearing at the output terminals of amplifiers PGA1-PGA3 is eliminated by using an automatic calibration circuit 117.
The automatic calibration circuit 117 comprises analog to digital converters 124A-124C, a register REG, digital to analog converters 125A-125C, and a counter 126. The analog to digital converters 124A-124C convert potential difference of the programmable gain amplifiers PGA1-PGA3 each into digital signals. The digital to analog converters 125A-125C gives input offsets to bring the DC offsets on the outputs thereof into zero to the differential inputs of the corresponding programmable gain amplifiers PGA1-PGA3 on the basis of the comparison results by the analog to digital converters 124A-124C. The counter 126 gives operation timing to each of the digital to analog converters 125A-125C.
According to the direct conversion receiver of FIG. 2, the dummy LNA 112B is activated during the DC offset elimination operation and, then, offsets are given to the differential inputs of the programmable gain amplifiers PGA1-PGA3 through the automatic calibration circuit 117. Consequently, DC offsets on the output terminals of the amplifiers PGA1-PGA3 are eliminated.
However, according to the direct conversion receiver of FIG. 2, DC offsets during only a time for the DC offset elimination operation are eliminated. Therefore, only the DC offsets by leakage of local oscillation signal LO are eliminated, while dynamic DC offsets such as those varying in accordance with the variation of gain of amplifiers. The dynamic DC offsets are amplified by amplifiers PGA1-PGA3, which results in the deterioration of the receiver""s performance. Additionally, since a dummy LNA 112B was used instead of LNA 112A to which radio input signal is inputted during the DC offset elimination operation, those DC offsets which vary in dependent on power level variation of the received radio signal are not eliminated.
Other technologies for solving the DC offset problem were introduced by U.S. Pat. Nos. 6,225,848 and 6,114,980.
According to U.S. Pat. Nos. 6,225,848 and 6,114,980, in order to eliminate DC offset on input of a gain stage, a sign bit generator, a binary search stage, and digital to analog converter are used. The gain stage amplifies DC offset between input signals. The amplified DC offset is inputted to the sign bit generator. The sign bit generator outputs either positive or negative sign bit according to the DC offset from the gain stage. The binary search stage determines the direction to which the DC offset may be corrected. Further, according to U.S. Pat. Nos. 6,225,848 and 6,114,980, DC offset is eliminated by forming a feedback loop.
However, in order to eliminate DC offset, it is required that the LNA amplifier at front-end of the receiver should be off. Therefore, DC offset which varies in accordance with power level of radio signal could not be eliminated.
The object of the present invention is to provide a correction circuit which may eliminate DC offset in real-time base.
Another object of the present invention is to provide a correction circuit which may eliminate DC offset which varies in accordance with the variations of frequency of local oscillation signal and cut off frequency of filters.
Another object of the present invention is to provide a correction circuit which may eliminate dynamic DC offset which varies in accordance with the variations of power level of the signal inputted to a signal processing apparatus.
Another object of the present invention is to provide a DC offset correction circuit which may eliminate DC offset in a tuner itself.
According to an aspect of the present invention, a signal processing apparatus for correcting DC offset in a communication system is provided. The signal processing apparatus comprises: a low noise amplifier (LNA) 301; a mixer 303 for mixing the output from said LNA 301 with local oscillation signal LO; a first offset correction amplifier 305 for amplifying output signal from said mixer 303 and for eliminating DC offset in the output signal in accordance with first control signal Vc31; a second offset correction amplifier 309 for amplifying output signal from said first offset correction amplifier 305 and for eliminating DC offset in the output signal in accordance with second control signal Vc32; a variable gain amplifier 311 for amplifying output from said second offset correction amplifier 309 wherein gain is controlled such that power level of output be maintained to a desired value; offset calibration mean 313 for calibrating DC offset in output from said variable gain amplifier 311; and offset correction mean 315 for outputting the first and second control signals Vc31 and Vc32 in accordance with the output from said offset calibration mean 313, to eliminate DC offset in the output from said variable gain amplifier 311.
According to another aspect of the present invention, a signal processing apparatus is provided, which comprises: a LNA 331; a mixer 333 for mixing the output from said LNA 331 with local oscillation signal LO; a first variable gain amplifier 337 for amplifying output from said LNA 331 while controlling the gain thereof; means connected to output of said first variable gain amplifier 337 for eliminating DC components in the output from said first variable gain amplifier 337; an offset correction amplifier 339 for amplifying output from said means for eliminating DC offset in the output in accordance with a first control signal; a second variable gain amplifier 341 for amplifying output from said offset correction amplifier 339 while controlling the gain thereof; offset calibration mean 343 for calibrating DC offset in output from said second variable gain amplifier 341; and offset correction mean 345 for outputting the control signal in accordance with output from said offset calibration mean 343, to eliminate DC offset in the output from said variable gain amplifier 341.
According to another aspect of the present invention, a signal processing apparatus is provided, which comprises: an offset correction amplifier for amplifying signals received to first and second input terminal differentially to output through first and second output terminals, respectively, and for eliminating DC offset in the received signals in accordance with a offset control signal; a variable gain amplifier for amplifying output of said offset correction amplifier while controlling gain thereof; offset calibration means for calibrating DC offset in output from said variable gain amplifier; and offset correction means for outputting the offset control signal for correcting DC offset calibrated by said offset calibration means.
According to another aspect of the present invention, a method for correcting DC offset in a signal processing apparatus is provided, which comprises steps of: activating the signal processing apparatus; setting initial data for correcting DC offset; sensing whether either frequency of PLL or cutoff frequency of LPF is changed; correcting DC offset, when a change is sensed in the sensing step, and determining the correction data from MSBs to LSBs n a successive approximation method; and correcting DC offset, when a change is not sensed in the sensing step or the correcting step is completed, by calibrating DC offset in a real time base and increasing or decreasing the correction data pursuant to the calibrated DC offset.
According to another aspect of the present invention, a method for correcting DC offset in a signal processing apparatus is provided, which comprises steps of: activating the signal processing apparatus; setting initial data for correcting DC offset; correcting DC offset and determining the correction data from MSBs to LSBs n a successive approximation method; and correcting DC offset by calibrating DC offset in a real time base and increasing or decreasing the correction data pursuant to the calibrated DC offset.